Multi-tasking transistor
Researchers at Pohang University of Science & Technology (POSTECH) developed a zinc oxide (ZnO) and tellurium (Te) heterojunction transistor expertise that displays detrimental differential transconductance (NDT), the place present decreases over a sure voltage vary.
By exactly controlling overlap size between the 2 supplies, the staff realized double detrimental differential transconductance (D-NDT), the place the phenomenon happens twice in succession inside a single system. This permits the system to carry out a number of circuit capabilities concurrently, doubtlessly simplifying circuit design and rising information processing pace.
The researchers applied a frequency quadrupler that converts one enter sign into 4 output alerts, a job that may usually require a number of transistors. In circuit experiments, the researchers discovered that information processing pace elevated fourfold inside a single enter sign cycle.
“This study demonstrates the possibility of implementing complex circuit functions at the level of a single device,” mentioned Byoung Hun Lee, a professor at POSTECH, in a press launch. “We expect this technology to be widely applicable to the development of ultra-compact AI devices and three-dimensional integrated, highly-density semiconductor systems.” [1]
P-bit fabrication
Researchers from Tohoku University and the National Institute of Standards and Technology (NIST) fabricated an built-in spintronic (*8*) (p-bit) on a silicon chip.
A key constructing block for probabilistic computer systems, the p-bit fluctuates stochastically between 0 and 1 by using intrinsic bodily randomness. Transistors and decrease interconnect layers have been fabricated on SkyWater’s 130nm CMOS course of, whereas superparamagnetic nanodevices and higher electrodes have been then built-in utilizing Tohoku’s spintronic system fabrication services.
In checks, the system demonstrated stochastic fluctuations of the output voltage over time and controllability of the time-averaged output via an enter voltage, two important traits for p-bit operation. The researchers imagine the method is a step towards large-scale sensible implementation of probabilistic computer systems. [2]
Tiny MoS2 nanotubes
Researchers from the University of Tokyo, National Institute of Advanced Industrial Science and Technology (AIST), Tokyo Metropolitan University, University of Tsukuba, and University of Osaka created 1nm broad single-walled semiconducting nanotubes made by rising molybdenum disulfide inside protecting tubes of boron nitride.
“We achieved the synthesis of atomically precise semiconducting nanotubes with nanometer diameters. The coaxial structure, where a semiconducting MoS2 nanotube is surrounded by an insulating boron nitride (BN) nanotube, is attractive for gate-all-around transistors, one of the most advanced transistor architectures,” mentioned Yusuke Nakanishi, an affiliate professor from the Department of Advanced Materials Science on the University of Tokyo, in a press release. “Our paper demonstrates a way for structural control of inorganic semiconducting nanotubes at the atomic scale. And we experimentally demonstrated that the bandgap of the nanotubes decreases as their diameters become smaller. […] Our nanotubes could offer a more reliable way to build ultrasmall semiconductor channels with consistent properties.”
Next, the researchers purpose to extend the nanotube size from the present restrict of a number of hundred nanometers to round 1 micrometer. [3]
References
[1] J. H. Jun, B. G. Kim, M. S. Kang, et al. “Multi-Functional ZnO–Te Heterojunction Devices Enabling Compact Frequency Quadrupler.” Advanced Functional Materials 36, no. 42 (2026): e74948. https://doi.org/10.1002/adfm.74948
[2] J.-Y. Yoon, N. Caçoilo, A. Madhavan, et al. 130-nm CMOS-integrated superparamagnetic tunnel junction-based p-bit, IEEE Electron Device Letters (2026). https://dx.doi.org/10.1109/led.2026.3696800
[3] Y. Nakanishi, R. Senga, A. Furusawa, et al. “Confined growth of armchair MoS2 nanotubes at the 1-nm limit,” Science: June 4, 2026 https://doi.org/10.1126/science.aee3446
Jesse Allen
Jesse Allen is the Knowledge Center administrator and a senior editor at Semiconductor Engineering.