According to a report by Xin Dongxi on July 1st, yesterday, Jiyiwei Semiconductor (Shanghai) Co., Ltd. (hereinafter referred to as “Jiyiwei”), a supplier of high-speed interconnection options, had its software for an preliminary public providing (IPO) on the Science and Technology Innovation Board accepted by the Shanghai Stock Exchange.
Jiyiwei was established on August 22, 2019, with its registered handle in Shanghai. It is a national-level key specialised and subtle “little giant” enterprise.
Before the IPO issuance, China Mobile Chain Leader Fund, National Artificial Intelligence Fund, and Second-phase Big Fund held 6.3%, 4.4%, and 1.41% of Jiyiwei’s shares respectively. Alibaba Cloud Computing and Tencent Venture Capital held 3.96% and 2.41% of the firm’s shares respectively.
Jiyiwei adopts a fabless enterprise mannequin and is primarily engaged in the analysis, improvement, design, and gross sales of high-speed interconnection chips, IPs, and associated personalized application-specific chips. The manufacturing course of is outsourced to main wafer foundries, packaging and testing distributors, and different suppliers in the trade.
The firm’s most important merchandise have successfully lowered China’s dependence on imported merchandise for high-speed interconnection chips and high-speed interconnection core IPs, and have fashioned an unbiased expertise resolution from core interconnection IPs to numerous sorts of interconnection chips.
In 2025, Jiyiwei launched a 224G SerDes IP that meets worldwide superior charges and achieved IP licensing. In the identical yr, the firm ranked first amongst home producers in the home market share of high-speed SerDes IPs with a single-channel price of 56G and above. Its industrialization course of is at the main stage in China and is at the forefront of the trade competing immediately with worldwide giants.
During the reporting interval, the firm’s high-speed interconnection SerDes IP merchandise have offered IP licensing companies to many main enterprises in the home AI knowledge heart trade and XPU trade, and have offered core connection expertise assist for AI clever computing chips, community switching chips, and many others.
Jiyiwei makes use of its self-developed core IP as the technical basis to full the unbiased analysis, improvement, and mass manufacturing of a number of chips, together with high-speed optical digital sign processing oDSP chips appropriate for 400G/800G optical modules and board-level relay Retimer chips supporting 400G/800G Ethernet transmission. Both merchandise have been industrialized.
The firm plans to raise 3 billion yuan on this IPO. Among them, 1.117 billion yuan will probably be invested in the analysis, improvement, and industrialization challenge of high-speed interconnection communication chips for the AI and knowledge heart fields. 806 million yuan will probably be invested in the analysis, improvement, and industrialization challenge of multi-scenario ASIC chips primarily based on high-speed interconnection and knowledge conversion core IPs. 645 million yuan will probably be used for cutting-edge expertise analysis and improvement initiatives, and 433 million yuan will probably be used to replenish working capital.
01. Revenue exceeded 700 million yuan in three years, and the gross revenue margins of high-speed interconnection IP and licensing enterprise both exceeded 90%
In 2023, 2024, and 2025, Jiyiwei’s revenues have been 16 million yuan, 310 million yuan, and 389 million yuan respectively, a progress of about 2256% in two years. The complete income in three years exceeded 700 million yuan. The web income have been -127 million yuan, -36 million yuan, and 13 million yuan respectively, turning losses into income. The R & D bills have been 128 million yuan, 184 million yuan, and 156 million yuan respectively.
Changes in Jiyiwei’s income, web revenue, and R & D bills (Charted by Xin Dongxi)
During the reporting interval, Jiyiwei’s most important enterprise income consisted of high-speed interconnection chip enterprise, personalized application-specific chip enterprise, high-speed interconnection IP licensing enterprise, and NRE (Non-Recurring Engineering) and different companies.
During the identical interval, the firm’s most important enterprise income primarily got here from the chip gross sales enterprise (together with high-speed interconnection chips and personalized application-specific chips). The most important chip gross sales revenues throughout the reporting interval have been 2 million yuan, 235 million yuan, and 277 million yuan respectively, accounting for 13.93%, 76.01%, and 71.37% respectively.
The progress of the firm’s most important chip gross sales income was due to the mass manufacturing of a number of chips equivalent to high-speed relay Retimer chips and personalized application-specific chips and the speedy enhance in downstream demand.
During the reporting interval, Jiyiwei’s revenues from high-speed interconnection IP licensing have been 3 million yuan, 74 million yuan, and 85 million yuan respectively, accounting for 18.75%, 23.99%, and 21.76% respectively.
During the reporting interval, Jiyiwei’s most important enterprise income all got here from the Chinese mainland, and there was no income from abroad areas.
During the reporting interval, Jiyiwei’s gross revenue margins for the most important enterprise have been 12.94%, 48.97%, and 42.4% respectively.
Among them, the gross revenue margins of high-speed relay Retimer chips have been 41.18%, 17.22%, and 25.9% respectively; the gross revenue margins of personalized application-specific chips have been 55.24%, 54.58%, and 39% respectively; the gross revenue margins of high-speed interconnection IP licensing have been 99.89%, 90.44%, and 90.63% respectively, which have been the highest in the identical interval.
In 2023, the high-speed relay Retimer chips have been nonetheless in the buyer introduction and threat mass manufacturing phases, and the promoting value of small batch check chips was comparatively excessive, leading to a comparatively excessive gross revenue margin. In 2024, this sort of chips entered large-scale mass manufacturing, the unit value elevated, the common value decreased, and the gross revenue margin decreased accordingly. After the mass manufacturing of personalized application-specific chips, the value decreased due to the scale impact, however in 2025, the firm gave corresponding value reductions to key main clients, and the gross revenue margin declined.
During every interval of the reporting interval, the firm’s gross revenue margin for high-speed interconnection IP licensing continued to keep a excessive stage, primarily as a result of the firm maintained sturdy market competitiveness in the course of of repeatedly enriching related product sorts, increasing purposes, and clients. At the identical time, this sort of enterprise is the licensing of self-developed core IPs, and the related prices are comparatively low, so the gross revenue margin is comparatively excessive.
The modifications in Jiyiwei’s gross revenue margin for the most important enterprise are as follows:
During the reporting interval, besides for 2023 when Jiyiwei’s gross sales scale was comparatively small, leading to a comparatively low gross revenue margin, the firm’s complete gross revenue margin was typically at the identical stage as that of comparable home corporations in the identical trade and decrease than the common of comparable abroad corporations in the identical trade.
02. R & D personnel account for up to 75%, and the most important merchandise function excessive pace and low bit error price
Jiyiwei’s most important merchandise function excessive pace, low bit error price, excessive reliability, excessive adaptability, and excessive flexibility. They are extensively utilized in fields equivalent to AI, knowledge facilities, community telecommunications, and wi-fi base stations. The particular state of affairs of the related merchandise is as follows:
The high-speed relay Retimer chip is a key sign enhancement part in the high-speed Ethernet transmission hyperlink. Its core features embody fixing the issues of attenuation and distortion throughout the long-distance transmission of high-speed indicators. The consultant composition structure of Jiyiwei’s self-developed single-channel 56G high-speed relay Retimer chip supporting 400G/800G Ethernet knowledge transmission is as follows:
(*3*)
The high-speed optical module is the core system in the optical communication system that realizes the conversion and transmission of optical and electrical indicators. Its inside construction might be divided into two core components: the optical chip group and the electrical chip group. The high-speed optical digital sign processing oDSP chip is the core part of the high-speed optical module.
As the core hub of the electrical chip group, the high-speed optical digital sign processing oDSP chip is primarily used to remedy numerous sign injury issues equivalent to sign attenuation and distortion throughout the photoelectric/electro – optical conversion and optical transmission processes. The consultant composition structure of Jiyiwei’s self-developed single-channel 112G high-speed optical digital sign processing oDSP chip utilized to 400G/800G high-speed optical modules is as follows:
Jiyiwei’s self-developed personalized application-specific ASIC chips are designed in accordance to the particular necessities of customers and the wants of particular digital methods. During the reporting interval, primarily based on related core applied sciences equivalent to SerDes, the firm offered clients with a number of personalized ASIC chip options. Taking the resolution for residence terminal gateways for instance, the consultant composition structure of this resolution is as follows:
The high-speed interconnection SerDes IP is the core class of semiconductor interface IPs. It is a pre-designed, verified, and reusable high-speed interconnection useful module.
The core precept of SerDes IP is to convert parallel knowledge into high-speed serial indicators for transmission, and carry out clock and knowledge restoration and serial-to-parallel knowledge conversion of high-speed serial indicators at the receiving finish. It performs equalization and compensation for numerous sign damages launched throughout the channel transmission course of, breaks by means of the bottleneck of high-speed sign transmission, and realizes environment friendly knowledge interplay between chips and between chips and exterior gadgets.
The consultant structure diagram of Jiyiwei’s self-developed DSP-based SerDes IP is as follows:
